This invention relates generally to instruction set computing. In particular the invention relates to reducing a set of instructions for execution on a processor. The invention also relates to expanding a set of reduced instructions.
Typical instruction set computing architectures use fixed length instructions. In many instructions only a subset of the total number of bits in the instruction are required to express the information content of the instruction. However, for the purpose of maintaining synchronisation with other instructions and the processor that is to execute the instruction set, each instruction has a fixed length defined by the particular protocol being used. Those bits of the instruction which are not used to express the information content of the instruction are left unencoded. Such instruction sets are inefficient because they use more bits than are necessary to carry the information content of the instructions.
As an example, some processors (for example those operating the reduced instruction set computer architecture MIPS-16) make use of prefixes. A prefix is an instruction which is associated with another instruction. A prefix contains the same number of bits as the instruction with which it is associated. For example, the MIPS-16 architecture uses short instructions each having 16 bits. Both an MIPS prefix and the MIPS instruction with which it is associated have 16 bits. Generally, a prefix extends the operand of the instruction with which it is associated. Often not all of the bits of the prefix are required to perform this function. However to retain alignment in the instruction set, the prefix maintains the same number of bits as the instruction with which it is associated. Those bits of the prefix required to perform the function of the prefix are encoded, and the remaining bits are left unencoded and ignored.
There is therefore a need to increase the efficiency of instruction sets whilst also maintaining synchronisation of the instructions within the instruction set such that a processor executing the instructions is also able to maintain synchronisation.